The era of ultra deep submicron ( UDSM ) design has come.

基于超深压微米设计的时代已经来临.

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The wire sizing method is an efficient solution to the interconnect optimization under deep submicron technology.

在深亚微米下,变线宽技术是互连线优化的一种有效方法.

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In this study, the strategy of ESD protection development in deep submicron process will be investigated.

本篇论文主要的目的是研究在深亚微米技术下的ESD防护设计策略.

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A resistance macromodel for deep - submicron process epi - type substrate based on the 2 D device simulation is presented.

摘要提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型.

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