Of course the sampling clock is itself a digital signal.

时钟本身也是数字信号,也会干扰模拟电路.

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The sampling clock generator must also have adequate spectral purity.

时钟发生电路固有的抖动应该足够小.

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Figure 5.36 shows the relationship between sampling clock jitter and SNR previously presented.

图5.36显示了采样时钟抖动和信噪比之间的关系.

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