D flip - flop with the main design of the timing circuit.

D触发器的设计主要用在时序电路中.

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Octal 3 state bus transceiver and D flip - flop. High - performance silicon - gate CMOS.

八路三态总线收发器和D触发器.谷高性能CMOS门.

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ECL OR - AND - gate can simplify a generalized ECL circuits structures, for example, an ECL double - edge - triggered D flip - flop.

作为常规 ECL 门的补充类型,常可用于简化一般ECL电路结构, 例如ECL双边沿D触发器.

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